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| DM74S280 9-Bit Parity Generator/Checker August 1986 Revised May 2000 DM74S280 9-Bit Parity Generator/Checker General Description These universal, nine-bit parity generators/checkers utilize Schottky-clamped TTL high-performance circuitry, and feature odd/even outputs to facilitate operation of either odd or even parity applications. The word-length capability is easily expanded by cascading. The DM74S280 can be used to upgrade the performance of most systems utilizing the DM74180 parity generator/ checker. Although the DM74S280 is implemented without expander inputs, the corresponding function is provided by the availability of all input at pin 4, and no internal connection at pin 3. This permits the DM74S280 to be substituted for the 180 in existing designs to produce an identical function, even if DM74S280's are mixed with existing 180's. Input buffers are provided so that each input represents only one normal 74S load, and full fan-out to 10 normal Series 74S loads is available from each of the outputs at low logic levels. A fan-out to 20 normal Series 74S loads is provided at high logic levels, to facilitate connection of unused inputs to used inputs. Features s Generates either odd or even parity for nine data lines s Cascadable for N-bits s Can be used to upgrade existing systems using MSI parity circuits s Typical data-to-output delay--14 ns Ordering Code: Order Number DM74S280M DM74S280N Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Connection Diagram Function Table Number of Inputs (A Thru I) that are HIGH 0, 2, 4, 6, 8 1, 3, 5, 7, 9 H L Outputs Even Odd L H (c) 2000 Fairchild Semiconductor Corporation DS006483 www.fairchildsemi.com DM74S280 Logic Diagram Typical Applications Three DM74S280's can be used to implement a 25-line parity generator/checker. This arrangement will provide parity in typically 25 ns. (See Figure 1.) Longer word lengths can be implemented by cascading DM74S280's. As shown in Figure 2, parity can be generated for word lengths up to 81 bits in typically 25 ns. FIGURE 1. 25-Line Parity/Generator Checker FIGURE 2. 81-Line Parity/Generator Checker www.fairchildsemi.com 2 DM74S280 Absolute Maximum Ratings(Note 1) Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 5.5V 0C to +70C -65C to +150C Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature 0 Parameter Min 4.75 2 0.8 -1 20 70 Nom 5 Max 5.25 Units V V V mA mA C Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL II IIH IIL IOS ICC Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current Conditions VCC = Min, II=-18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL =Max VIH = Min, VIL = Max VCC = Max, VI = 5.5V VCC = Max, VI = 2.7V VCC = Max, VI = 0.5V VCC = Max (Note 3) VCC Max (Note 4) -40 67 2.7 3.4 0.5 1 50 -2 -100 105 Min Typ (Note 2) Max -1.2 Units V V V mA A mA mA mA Note 2: All typicals are at VCC = 5V, TA = 25C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 4: ICC is measured with all inputs grounded and all outputs OPEN. Switching Characteristics at VCC = 5V and TA = 25C RL = 280 Symbol Parameter From (Input) To (Output) tPLH tPHL tPLH tPHL Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Data to Even Data to Even Data to Odd Data to Odd CL = 15 pF Min Max 21 18 21 18 RL = 280 CL = 50 pF Min Max 24 21 24 21 ns ns ns ns Units 3 www.fairchildsemi.com DM74S280 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A www.fairchildsemi.com 4 DM74S280 9-Bit Parity Generator/Checker Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com |
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